With increasing demands for embedded memory type structures, mixed-signal circuits, and system on chip (SOC) IC design, it has become necessary to form multiple transistor structures on a single die to achieve integrated functioning of the different transistor structures. For example, transistors with different structures and functions typically operate under different current and voltage parameters requiring different processing steps for the various transistors. For example, in the formation of high Voltage MOSFETS, for example operating at Voltages higher than about 30 Volts, for example, about 40 to about 60 Volts, the gate oxide is required to be much thicker for proper operation and to avoid dielectric breakdown.
On the other hand, split gate flash memory MOSFETS require oxide layers which involve thermal processing cycles including oxide and nitride depositions that are incompatible with the formation of other types of transistors formed on the same process wafer and within the same die, for example in embedded memory applications, including high voltage MOSFETS. The incompatible processes require different and separate processing steps which add to the cost of production including increased cycle time to decrease wafer throughput. In addition, the thermal cycles required by separate process may have an adverse effect on different types of transistors, for example by undesirably subjecting one transistor type in the embedded or integrated device to thermal cycling processes which have an adverse effect on, for example, dopant profiles, thereby altering electrical properties.
Thus, there is a need in the semiconductor manufacturing art for improved processing methods for integrating the processing methods for the formation of embedded devices to increase throughput and improved device reliability.
It is therefore an object of the invention to provide an improved processing method for integrating the processing methods for the formation of embedded devices including high Voltage MOSFETS and split gate flash memory to increase throughput and improved device reliability while overcoming other shortcomings and deficiencies of the prior art.